PRIYANKA SISTLA

*** ********* **, *** *-*, Columbus, OH 43202

Cell: +1-650-***-****, Email: ac6f2o@r.postjobfree.com

OBJECTIVE

A highly motivated Electrical engineering graduate who is a team player and has a constant thirst to keep learning. Currently looking for full-time and internship opportunities.

EDUCATION

Master of Science in Electrical & Computer Engineering August 2016 - December 2017 The Ohio State University, Columbus, Ohio GPA: 3.4/4 Bachelor of Engineering in Electronics & Communication Engineering Aug 2012 – June 2016 SRM University, India GPA: 3.6/4

TECHNICAL SKILLS

• Languages : C, C++, VHDL, Verilog, Assembly Level, MATLAB, Linux Scripting, Perl (Elementary Level)

• Platforms : Windows, Linux

• Tools : Cadence, Xilinx ISE, MATLAB, ModelSim (Intel FPGA), Quartus Prime, TopSPICE, FIO, Vdbench, HDParm RELEVANT COURSES

Graduate: Mixed Signal VLSI, HDL Verification, Computer Architecture, Image processing, Probability and Random variables, Linear Algebra in finite dimensions, Project Management, Computer Vision. Undergraduate: VLSI Devices & Design, Electronic Devices, Digital Logic Design, Linear Integrated Circuits, Microprocessors & Microcontrollers, Embedded Systems

PROFESSIONAL EXPERIENCE

Application Engineering Intern, Intel Corporation, Folsom CA May 2017 – August 2017

• Drove performance testing, firmware debugging and supported customer solution development of data center and client SSDs for top global customers

• Collaborated with Failure Analysis teams to identify and rectify the errors associated with various data center and client SSDs.

• Developed content, including co-authoring a whitepaper and spearheading a remote server demo, that was integral to customer adoption of new Intel SSDs (S3520, S4500, S4600)

• Prepared a hands-on lab and guide for Intel’s Technical Solutions Training, a series of global-reaching events for 100 top channel customers.

RESEARCH PROJECTS

Runtime detection and diagnosis of soft hangs for smartphone apps May 2018 - Present

• Analyzing android apps that show soft hangs using Android studio and then checking if the soft hangs are persistent with different patterns of operation.

ACADEMIC PROJECTS

Design of Address decoder for 64x32 bit SRAM using Cadence Virtuoso Mixed Signal VLSI

• Designed and implemented an optimized address decoder for a 32-bit SRAM circuit. Layout based on 0.18um TSMC technology with DRC and LVS Checks

Propagation Delay Analysis of a F04 Inverter chain and 5-stage Ring Oscillator Mixed Signal VLSI

• Analyzed the propagation delay, rise time and fall time along with the sizing of the transistors for obtaining a desirable output and optimum delay time. The analysis was done using Cadence Virtuoso Analysis of a latch-up circuit Mixed Signal VLSI

• Analyzed latch-up by modeling n-type and p-type inverters using MOSFET and varying the load resistance with parametric step in TopSPICE.

Design and Verification of Pipelined Floating point Adder/Multiplier HDL Verification

• Designed and exhaustively verified a single precision floating point adder/multiplier in VHDL using ModelSim (Intel FPGA). Generated test vectors using C Coding and tested exhaustively to account for all boundary conditions Design and implementation of a 16-bit ALU HDL Verification

• Designed and implemented a 16-bit ALU using various generic units with different architectures. Used VHDL to simulate and verify the same using ModelSim

SAR Based Analog to Digital Converter HDL Verification

• Developed a State Machine for successive approximation analog to digital converter using VHDL ModelSim simulator. Employed a handshake protocol for the conversion process.

Implementation of Instruction set for OSIAC Computer Computer Architecture

• Developed and implemented instruction set using microinstructions and a test case to check their execution on OSIAC system Recovering the static background and tracking the foreground of an image Computer Vision

• Recovered the static background and displayed the image with the background subtracted using Robust Principal Component Analysis (RPCA) on a set of images in MATLAB.

Implementation of SIFT and Optical Flow Image Processing

• Provided feature matching and described the motion field for a given set of images in MATLAB. 3D structure reconstruction using Affine Structure from Motion Image Processing

• Abstracted original image using a given set of images by implementing Affine Structure from Motion in MATLAB.

Contact this candidate