Shweta Sharma

CONTACT D-*/*, RADIO COLONY, VOICE (0-897*******

INFORMATION Near GTB nagar metro station E-mail ac39cp@r.postjobfree.com

New delhi-110009 ID

OBJECTIVE Seeking full time entry-level position in the field of Analog/RF/Mixed Signal

Design, Digital System Design or ASIC Design.

AREAS OF Analog/RF Mixed Signal Design

FOCUS Digital System Design

ASIC Design

EDUCATION Master of Technology in VLSI Design (Jun 2011 – Jun 2014)

Malviya National Institute of Technology, Jaipur GPA: 7.14/10.00

RF Integrated Circuits Analog and Mixed Signal Ics

System Level Design & Modeling Digital System Design

Digital CMOS Ics CAD Algo. for VLSI Physical Design

Bachelor of Engineering in Electronics & Comm Engg. (Aug2003-May2007)

University of Rajasthan, Jaipur AGGREGATE: 65.2/100

Analog Electronics Linear Integrated Circuits

Digital Logic Design Digital Signal Processing

Microprocessors & Microcontrollers Communication Systems

SKILLS Tools: Cadence- Virtuoso, Assura, Encounter, HSPICE, Matlab, Modelsim,

Xilinx ISE, Eclipse, Octave.

Languages: System Verilog HDL, VHDL, Verilog HDL, SystemC,

SystemC-AMS, Perl, Python, C++

Operating Systems: Linux, Windows

RESEARCH System Level Modeling of Analog and Mixed Signals, Case Study of IEEE

802.11 Wireless RF Transceiver. (Jul 2013 – May 2014)

High Level Modeling of RF Transceiver on Architectural Level by using SystemC-AMS, attain faster simulation speed compare to SPICE.

Obtain time and frequency domain behaviour of system, better than MATLAB.

Reduce noise and DC offset cancellations and overcome the limitations of components such as ADC, DAC, LNA, PLL etc.

PROJECTS Design of Sequential and Combinational Circuits Using Reversible Logic

Gates (using SPICE)

Design and Implement Adders,encoders, Flip flops by using reversible logic.

Attain no memory loss as compare to non reversible technology.

Design of a 2-bit multi-valued ADC in 180nm Digital CMOS (using

CADENCE)

Design and layout a 2-bit higher radic A-toD converter circuit consisting of a combination of pipeline ADC which generate multi-valued logic outputs using 180nm Technology.

Design and implementation of 32-bit MIPS in VHDL (using Modelsim and

Xilinx ISE)

Code 32-bit MIPS in VHDL, simulate it by test bench and implement it on CPLD and SPARTAN 3E.

Also design it in assembly language and test its performance using SPIM SIMULATOR.

Design and Implementation of UART using VHDL (using Xilinx ISE and FPGA

Board)

Design, synthesize and simlulate the code for UART in VHDL on Xilinx ISE.

Further implemented the code by using JTAG on SPARTAN 3E on FPGA Board.

Design and Implementation of Digital Clock using VHDL (using Modelsim and

FPGA Board)

Design a digital clock, simulate it using test bench and further implement it on SPARTAN 3E.

WORK Assistant Professor, CMR Institute of Technology, Bangalore(Karnataka)

EXPERIENCE Duration: 22th july 2015 to 31st may 2016

Subjects Taught: Embedded System Design, Digital Logic Design, VLSI Design,

Communication Systems

Assistant Professor, Swami Keshvanad Institute of Technology, Jaipur (Raj.)

Duration: 26th july 2010 to 18th nov 2013

Subjects Taught: Embedded System Design, Digital Logic Design, VLSI Design,

Communication Systems

Lecturer, Institute of Engineering and Techonology, Alwar (Raj.)

Duration: 1st june 2008 to 25th july 2010

Subjects Taught: Microprocessor and Microcontrollers, Electronic Devices and

Circuits, Analog Electronics, Signals and Systems

Lecturer, Ajmer Institute of Technology, Ajmer (Raj.)

Duration: 19th august 2007 to 31st may 2008

Subjects Taught: Linear Integrated Circuits, Communication Systems, Digital

Signal Processing, Electronic Devices and Circuits.

CONFEREN- Presented Paper, “Design of Arithmetic Circuits Using Reversible Logic Gates”,

CES AND in National Conference on Advancements in Microelectronic and

WORKSHOPS Communication Technologies, 15 th -17 th March 2013 at SKITM&G, Jaipur.

Attended Workshop (2 Weeks), Advance Faculty Development Program on

Hardware and Firmware design for ARM based Embedded Systems at CDAC,

Hyderabad in June, 2012.

Attended Conference IETE conference on Advances in Wireless & Optical

Communication systems, AWOCS- 2012 on 17 -18, March, 2012 in SKITM&G,

Jaipur.

Attended Conference and Tutorials on Reverse Engineering and System design

using SystemC-AMS in International conference on VLSI Design and Embedded

System, 7 th - 11 th Jan, 2012 at HICC, Hyderabad.

Attended Faculy Development Program in Jan. 2011 at SKITM&G, Jaipur.

HONORS Awarded Silver Level in Software Testing in 'Clue - 2006' held at M.L.V Textile

& Engg. College, Bhilwara.

Awarded Scholarship in 'Samwad Abhivayakti Pratiyogita' in2003.

Awarded Gargi Puruskar in 10th Board for excellence in performance.

Awarded 2nd Position in ' District Level Badminton Competition' at Nagaur in

2001.

REFERENCES Dr. Vineet Sahula Dr. Lava Bhargava

Professor & Head Associate Professor

Malviya National Malviya National

Institute of Technology Institute of Technology

Jaipur, Rajasthan Jaipur, Rajasthan

Cell: 094******** Cell: 094********

Email: ac39cp@r.postjobfree.com Email: ac39cp@r.postjobfree.com

(SHWETA SHARMA)

Contact this candidate