Venkatesh.P

Address:

H-No:*-**(a),

Joharapuram,

Aspari, Kurnool Email Id:

abue5s@r.postjobfree.com

Andhra Pradesh Mobile :

888-***-****

Career Objective:

To see my ideas take the shape of reality and to utilize my

skills to the fullest in order to develop novel, robust and powerful

solutions and thus benefit the organization I work for.

Professional Qualifications:

> Electronics and Communication Engineering at Gurunanak Eng. College,

Hyderabad

> Strong knowledge on C, C++

> Strong skills in using OOPS concepts with secure coding practices.

> Good communication and documentation skills, proven ability to work on

multiple tasks concurrently completing them with in time.

> Committed team player with interest and zeal to learn new skills and

technologies.

> Good understanding of the ASIC and FPGA design flow.

> Advanced VLSI Design & Verification Certification at Maven Silicon,

Bangalore

> Very good knowledge in verification methodologies.

> Experience in using industry standard EDA tools for the front-end

design andverification.

Academic Profile:

Course Duration School/College Board/University Percenta

ge

Secondary 2006 Sri Vidya High School of Secondary 57.16

Education School Education

Intermediat 2006-2008 Narayana Junior Board Of Intermediate 81.4

e College Education

(M.P.C)

B-Tech 2008-2012 Guru Nanak Jawharlal Nehru 66.18

(E.C.E) Engineering Technological

College University

Technical Skills:

Languages : C, C++, Perlcirpt

Operating Systems : Windows XP, Windows 7, Linux

Tools : MATLAB, Active HDL

VLSI Domain Skills:

HDLs : Verilog and VHDL

HVL : SystemVerilog and PSL

TB Methodology : UVM and OVM

EDA Tools : Modelsim and ISE

Domain : ASIC/FPGA Design Flow, Digital Design

methodologies

Verification Methodologies : Coverage Driven Verification, Assertion

Based Verification

Knowledge : Digital Design, RTL Coding,

FSM based design, Simulation, Code Coverage, Functional Coverage,

Synthesis, Static Timing Analysis, ABV, Telecom protocols like GSM, CDMA,

etc...

Certifications Done:

> Advanced VLSI Design Certification at Maven Silicon during Nov 2012-

March 2013

> Advanced VLSI Verification Certification at Maven Silicon during Nov

2012- March 2013

> Matlab Certification at Gurunanak Eng. College, Hyderabad during April

- June 2011

> Computer Hardware certification at Real Point Institute, Adoni

> C programming certification at Real Point training Institute, Adoni

> C++ programming certification at Real Point training institute, Adoni

Projects Done:

Project #1

Title: Development of Coal Mine Safety System Using Wireless Sensor Network

Description : As of now there are very minimal measures taken for the

security of the ground crew working in the Coal Mines. This toolkit helps

the ground crew to monitor and alert the workers with the underground

conditions such as temperature, gaseous levels and other major

catastrophic conditions which can lead to loss of life.

The underground section sensors will senseMore >>sensesessssssss the

environment conditions such as temperature, humidity, gas etc.., and this

information is sent through zigbee transmitter to ground section. The

zigbee receiver takes this information and sends it through GSM modem which

will display the alert on an LCD. Here the GSM modem also sends a message

to registered mobile subscribe thereby avoiding the dangerous accidents.

Duration: 4 Months

Roles & Responsibilities: Involved in design, development and testing

phases of the project thereby ensuring quality and reliability of the

toolkit.

Project #2:

Real Time Clock - RTL Design and Verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa - Verification Platform and ISE

> Implemented the Real Time Clock using Verilog HDL independently

> Architected the class based verification environment using

SystemVerilog

> Verified the RTL model using SystemVerilog.

> Generated functional and code coverage for the RTL verification sign-

off

> Synthesized the design

Project #3:

Dual Port RAM - Verification

HVL: System Verilog

EDA Tools: Modelsim, Questa - Verification Platform and ISE

> Implemented the Dual Port Ram using Verilog HDL independently

> Architected the class based verification environment using system

Verilog

> Verified the RTL module using System Verilog

> Generated functional and code coverage for the RTL verification sign-

off

Personality Traits:

> Quick Learner

> Good Team player and can works independently too

> Good at Analysing issues and proposing feasible solutions

Declaration:

I do hereby declare that the particulars of information and facts stated

herein above are true, correct and complete to the best of my knowledge

and belief.

Place: Bangalore

Date: 07/05/2013

(P.Venkatesh)

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