Nima Homayoun Nima Homayoun

W: 408-***-****

System Architect Engineer, Corporation, Santa Clara, CA, 08/96 - present

Researching on future mobile platform voltage roadmaps through year 2001.

Working on the power management features of the Next Pentium Pro Chipset (North Bridge).

Conducting Platform Power Management Techniques training course across several intel sites.

Senior Design Engineer, Corporation, Santa Clara, CA, 09/95 - 08/96

Involved on the architectural definition, wrote the PCI interface testplan and validated a

PCI-to-PCI Docking station bridge Chipset -

Wrote an Automatic Test Generation utility in Perl to generate PCI-to-PCI diagnostics.

Architect the process for the department Intranet and supervised its first implemention.

Design Engineer, Corporation, Santa Clara, CA, 09/93 - 09/94

Designed a Low-power Pentium Chipset - PCIset

Wrote VHDL code and tested several fubs - PCIset

Gate level Validation of a Pentium Chipset using Verilog_XL - Product (Neptune Project)

Design Engineer, Corporation, Folsom, CA, 05/93 - 09/93

Modified HDL code in the paging and segmentation unit of a microprocessor profilation.

Verified the functionality of the above fubs using Zycad Engine.

Research/Teaching Assistant, Dept. of Engineering, U. of Wisconsin-Madison, 8/91-5/93

Developed an Event-Driven real time simulator in C++.

Derived mathematical expressions for optimal Mean Response Time.

Conducted junior level digital electronics and circuit laboratories.

Firmware Engineer, Electronic Devices Inc. Chesapeake, Virginia, 5/90-8/91

Built and tested a digital Depth Finder test set unit used for navigation purposes.

Implemented a front-end program for PADS2000 commercial software., 4 graduate course in IE Program 1994,1995

Master of Science in Electrical Engineering, University of, May 1993 .

Bachelor of Science in Computer Engineering, Minoring in Physics., May 1991 .

Publications"Accelerated Graphics Port (AGP) Busy signal in Mobile systems," Internal Confidential Document, Spring 1997.

"Dual Well Design/Validation techniques in Mobile Chipset Design," white paper, Summer 1996.

"Dynamic Priority Scheduling of Aperiodic Tasks in Hard Real-Time Systems,"

IEEE Transaction on Real-time Systems, September 1993.

"The effect of pendal electrons on breakdown and sustainment of hollow cathode discharge",

IEEE International Conference on Plasma Science, May 1990.

SkillsLanguages:,, C/C++, Verilog and HTML.

Asic Tools:, Verilog_XL, Vantage, and Engine.

Intel Tools:

iHDL, CSE, DylinkII, SEES, SALT

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