Jayalakshmana Kumar Pragasam

****, ****** **., ***. #*,

Mountain View, CA 94040

Tel: 650-***-****(H) 650-***-****(W)

Email:abqgnf@r.postjobfree.com

URL:

http://www.ece.vill.edu/~pragasam

OBJECTIVE

A challenging full time position in IC design involved in various stages of the top-down design pipeline.(RTL-gdsii).

COMPUTER SKILLS EDA tools: Design Compiler, Prime-Time, VCS, Design System, Arcadia (Synopsys), DFII, Gate Ensemble, Silicon Ensemble, Dracula (Cadence), Apollo (Avanti) and most of the front end

Mentor Tools.

Languages: C, C++, VHDL, GENIE (Mentor's Language for Le), UNIX

shell, HTML, DLX assembly.OS/Environments: Unix (Solaris 2.x), Windows 3.x, 95,

NT

EXPERIENCEAug '98 - present:

Senior Engineer (R&D), Synopsys Inc.

Presently working in the library development for

Standard Cells and Cell Based Arrays. Starts with the characterization of core, memory, IO

cells (Arcadia and HSPICE), integrating them together into a library

and taking them through a full RTL-GDSII QA flow by synthesizing a

test design in RTL into a gate level netlist (Design Compiler), P&R the synthesized design (Silicon Ensemble and Apollo), DRC&LVS physical verification of the routed design

(Dracula, Calibre), extraction of parasitics (Arcadia) and finally back-annotating for timing closure (Prime Time).

Also played a key role in the team by driving several process improvements (PAE), disseminating critical information and representing the team in external forums (Corporate Quality Measures)Jan '98 - Aug '98:

Research Assistant, ECE Department, Villanova University.

Worked on the Image Analysis of a heart movement in a MIDCAB surgery

for Lenox-Hill hospital, NY.Aug '97 - Dec '97:

Teaching Assistant, ECE Department, Villanova University.

Duties included grading assignments, conducting and evaluating lab sessions

in Signal ProcessingJul '96 - Dec '96:

Engineer, Software Design, SIEMENS Communicaton Software Ltd., Bangalore,

India.

Member of the object oriented design team that worked with the engineers from the headoffice in Munich, Germany in the development of a software

called COSIMA (COmmunication SIte MAnagement) for complete monitoring of

the EWSD exchanges of Siemens Ltd., worldwide.

PROJECTSDeveloping standard cell libraries for various customers according to their specifications

at Synopsys. Currently working on DSM (150 nm) libraries.

The QA phase is framed to emulate a real design flow wherein a RTL netlist

is taken into DC to get a gate level netlist targeting our library with area or timing constraints,

which is then fed into SE or Apollo for Place and Route and the design

physically verified using Dracula and Calibre. Parasitics are extracted

using Arcadia and then back-annotated into PrimeTime. Benchmarking is done against various libraries in the same technology and also between our own libraries in different technologies.

A top-down vertical realization of the 8051 microcontroller design from the RTL level

targeting Synopsys' 0.18( library, optimized for area. Placed and routed the design,

inserted clock trees and did a Physical verification (DRC/LVS/ANT) in Dracula. Generated the

back-end netlist, extracted the parasitics in Arcadia and delivered a DSPF file for

back-annotation.Sole contributor in the analysis and implementation procedures for the advanced Process

Antenna Effect (PAE) modeling techniques. Analyzed the process specification, investigated

and framed out the implementation routines, tested the methodology in a test chip and

formulated the flow guidelines. Got special appreciation from the Director of R&D for this

work.RTL design of a complete 32 bit 5 stage pipelined

DLX RISC processor(Datapath and Control Unit) incorporating hazard

detection, forwarding, pipeline stalls and delayed branches, implementation

of the design using VHDL behavioral models and schematics and simulation

of the top level structural models using test beds.Design of a memory system for the DLX RISC processor with separate

Instruction and Data Caches (LRU), DRAM and cache controller, and implementation

of these in VHDL. A generic Cache, capable of working in any of the configurations

(Direct Mapped, n way Set Associative, Fully Associative) was designed

and was integrated with the datapath and control unit, tested and compared

using an assembly code. (Hyper

text report)Design of the complete datapath of the DLX processor

with transistor level schematics and full custom VLSI circuit layout

of the design using 2LM, single poly, 1.2 micron CMOS technology.

EDUCATION Jan '97- Jul '98

M.S. in Electrical Engineering, Villanova University, Villanova, PA.

Curriculum:

GPA: 4.0/4.0

Advanced Computer Architecture

Object Oriented Programming

VLSI design Advanced

Digital Signal Processing.

Neural Networks Image

Processing

Communication Systems Statistical

Signal ProcessingAug '92 - May '96

B.E. in Electrical & Electronics Engineering, Anna University,

India.

Curriculum:

Cumulative

GPA: 9.0/10.0

Basic courses in Digital Systems, Microprocessors, ICs, Microprocessors

in Power Electronics, Object Oriented Programming and Communication Engineering.

ACCOMPLISHMENTS Selected to be a member of the Excellence Team within Synopsys, which has the whole

responsibility in testing and ensuring the quality of libraries before it gets signed off to

the customer by the top-level management. This involves professional attention to the

details not only in the technical spectrum, but also in every aspect of the product.

Rated as a performer beyond expectations at Synopsys for my consistency in delivering

quality results and for my quest to refine processes that are obsolete.

Was awarded the University Gold Medal for two consecutive years for academic excellence.

ACTIVITIES Student representative in the Class Committee Meeting for two years

which involved the responsibility of course planning with the faculty members

based on the students' feedback. Captained the winning team in college cricket and got the District

level best player award in Table Tennis from the Rotary Club of India.

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