Assistant Design

Grama Srinath Shreyas

abq1bs@r.postjobfree.com

Cell: +886-********* (Taiwan)

SYNOPSIS

Intern at Vanguard International Semiconductor Corporation, Hsinchu Science Park,

Taiwan, Jul’ 12 – Sep’ 12.

Intern at Vanguard International Semiconductor Corporation, Hsinchu Science Park,

Taiwan, Jan’ 13 – present.

Familiar with Cadence Tools (Virtuoso layout editor, DRC, LVS and ADE) along with SKILL

programming.

1 year and 6 months of industry experience in Semiconductor Technology as Research

Assistant for TSMC and VIS under the guidance of Professor Dr. Gene Sheu in Centre for

Computational Microelectronics, Asia University, Taiwan, Sep’ 11 – Present.

Experience in TCAD simulation using SYNOPSYS (Taurus TSUPREM-4, Medici, Sentaurus

Process, Sentaurus Device, and Sentaurus Structure Editor) for development and optimization

of Semiconductor processes and devices.

EDUCATIONAL QUALIFICATION

MS, Microelectronics Asia University, Taichung, Taiwan

(Semiconductor Technology) Sep’ 11 – Jun’2013 (expected)

B.E, Telecommunication Engineering P.E.S.I.T, Aug’ 07 – Jul’ 11

With a GPA of 8.02/10

INTERN, VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION, HSINCHU SCIENCE PARK, TAIWAN,

JUL’12 – SEP’12 & JAN’13 - PRESENT

JUL’12 – SEP’12

Understanding the following Documents: PDK (Product Design Kit) Documents, SPICE Model

Card, DRC (Design Rule Check) file, LVS (Layout Verses Schematic) file, CDF (Component

Description Format) file and GDS (Graphic Data System) files.

Automated extraction of selected data from the above mentioned documents using PERL

UIS test measurement using Unclamped Inductive Load tester ITC-55100 and Switching

Inductor Matrix ITC-55140.

Wafer-level measurements and data analysis using Semi-automatic prober (Cascade), Agilent

B1500.

JAN’13 – PRESENT

Working in PDK team under CDS (Customer Design Support) Dept.

Assigned a role to create and update the PDK documents with the help of cadence

environment.

RESEARCH ASSISTANT, CENTRE FOR COMPUTATIONAL MICROELECTRONICS, ASIA UNIVERSITY, TAIWAN,

SEP’11 - PRESENT

Development of SOI/JI Lateral IGBT for High Voltage and High Power IC.

Development and optimization of High Voltage Super-junction MOSFET cell and its junction

termination structure.

Deducing an analytical model for reliability issues during Unclamped Inductive Switching (UIS)

stress in Power MOSFET circuit applications.

Threshold voltage fluctuations in Zener diodes using IFM(Impedance Field Method) simulation

using RDF( Random Dopant Fluctuations)

Thermal SOA and Energy Handling Capability of LDMOS Device.

Familiar with simulation of electrical characteristics (I-V, HBM stress, TLP) of MOS devices and

circuit simulation of MOSFET employed circuits in TCAD.

PUBLICATIONS

“Unclamped Inductive Switching Stress failure Mechanism of LDMOS”, - Vijay Kumar M P,

Grama Srinath Shreyas, Chinmoy Khaund, Shao-Ming Yang and Gene Sheu, IEEE EDSSC-

2013, Hongkong.

“Failure and Ruggedness Investigation in LDMOS under Unclamped Inductive Switching (UIS)

conditions” – Shao-Ming Yang, Grama Srinath Shreyas, Chinmoy Khaund, Vijay Kumar M P,

Karuna Nidhi, Neelam Agarwal and Gene Sheu (Submitted to Microelectronics Reliability-

2013).

“Optimization of Forward Voltage Drop and Turn-off Energy Loss for 700V LIGBT”, - Jaipal

Reddy, Vijay Kumar M P, Grama Srinath Shreyas, Shao-Ming Yang, Gene Sheu (Submitted to

SISPAD-2013).

“Effect of trench depth and trench angle in a high voltage polyflanked - super junction

MOSFET”, - Chinmoy Khaund, Vijay Kumar M P, Grama Srinath Shreyas, Karuna Nidhi, Neelam

Agarwal, Shao-Ming Yang and Gene Sheu (Submitted to SISPAD-2013).

TECHNICAL PROFICIENCY

Cadence Tools (Virtuoso layout and schematic editor, DRC, LVS and ADE) and SKILL

Tools

programming

Process Simulation tools - Taurus TSUPREM-4, Sentaurus Process and Athena

Device Simulation tools - Taurus Medici (2D), Sentaurus Device (2D and 3D) and Atlas

Sentaurus Structure Editor - Tool for creating geometric structure for TCAD simulation

HSPICE, MATLAB, XILINX, Keil, Tanner EDA

Programming PERL, Embedded C, C,C++, VHDL, Verilog, DSP algorithms and Assembly Level

Languages language

Hands-on Semi-automatic prober (Cascade), Agilent B1500, HP4156C, Unclamped Inductive Load

equipments tester ITC-55100, Switching matrix ITC-55140, Keithley 4200 SCS, Celestron TLP set-

up and FPGA.

PERSONAL DETAILS

Name: Grama Srinath Shreyas

Father’s Name: G.N.Srinath

Languages Known: English, Hindi, Kannada, Tamil, Telugu and Basic Chinese.

GF-1, Shanthi Nivas, Shivraj Residency, BEML 3rd stage, Rajarajeshwari

Permanent Address:

Nagar, Bangalore.

Local Address: No. 500, Lioufeng Rd, Wufeng, Taichung County 41354, Taiwan (R.O.C)

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