SACHIN RAJ AGGARWAL

M.Tech (VLSI); ASIC, FPGA, Analog Design/Verification

Contact Phone e-mail Id -

Mobile - (91) abnxqv@r.postjobfree.com

928-***-****

(91-925******* abnxqv@r.postjobfree.com

Aspiring to pursue assignments in the domain of Semiconductor &

Electronics Engineering with a growth oriented organization of repute and

to Explore VLSI Design - ASIC Design & Verification

Career Profile

Technical Skills / IT forte

Area of Interest ASIC Design(Frontend & Backend) / Verification,

FPGA, RTL Coding, Self Testing Testbench,

Testcase development & regression testing.

HDLs / HVL C/C++, Verilog, VHDL, Verilog, systemVerilog

Scripting Languages Perl, Python, Tcl, Shell

Operating Systems Windows XP/ 2000, Linux(CentOS-5.2),, Unix

(basic)

VLSI / EDA tools Tanner EDA Tools, IC Station(Schematic, Layout

Editor, LVS, DRV, SDL), Model Sim 6.5, Matlab,

Hardware Field Digital Design, Analog Design, Circuit Design

EXECUTIVE SUMMARY

< 1+ Years Digital Design & Verification experience with Incise Infotech as

Grad.Engg.Tr.

< Expertise in Design and Verification.

< Expertise in Verilog, System Verilog, C.

< Worked on - AMBA AHB bus interface, Timer, FIFO, Round robin Arbiter

Design & ver.

< Design, RTL Coding, Self Testing Testbench, Testcase development &

regression testing.

< M.Tech. (VLSI) from C-Dac, Noida under GGSIP University, Delhi

< B.Tech. (Electronics & Comm. Engg.) from HMRITM under GGSIP University,

Delhi.

< Adaptable and a quick learner; possesses skills to work under pressure.

< Possess strong management, communication & interpersonal skills.

< Areas of Interests - ASIC, FPGA, Designing, RTL Coding, Verification,

OVM, UVM, VMM, tcl, Perl, Python, Matlab, Mentor

Graphics/Cadence/Synopsys Tools.

?Work Experience (approx.12months) ?

Designation Organization Duties Joining Remarks

Date

Graduate INCISE INFOTECH Trainee VLSI VLSI, Verilog,

Engineer P. LTD., NOIDA Designing Aug.,10-Ju EDA Tools

Tr. ly,11

Projects undertaken: " Designing of AMBA using Verilog, FOUR PORT

switch, 3 mode Timer, Synchronous & Symmetric FIFO." Using systems

Verilog, Perl and Modelsim6.5

Technical CETPA INFOTECH P. To train B. @

Trainer LTD., NOIDA Tech June,10-Ju Rs.10000/-p.m.

students in ly,10

C, C++

Contractual job of 2 months - got appraisals & accolades from

Management & Students.

Academics

Gate qualified (Gate examination 2011 qualified)

YEAR OF PASSING GATE SCORE GATE PERCENTILE ALL INDIA RANK

2011 456 94.80 7126

EDUCATIONAL QUALIFICATIONS -

Degree Period Institute Percentage

(University/Board)

M. Tech. (VLSI) GGSIPU, 2011-13 C-DAC, NOIDA 72% Up to 2nd

Delhi Sem.

B. Tech. (ECE) GGSIPU, 2006-10 HMRITM, Delhi 70.48 %

Delhi

XII (under 10+2 ) CBSE 2004-05 SBKV Sr. Sec. 85.6 %

School

X (under 10+2) CBSE 2002-03 SBKV Sr. Sec. 65.8 %

School

Thesis/Projects

M.Tech Projects/Training

M. Tech Minor Project

Title Single Bit Dual Port SRAM Cell Design

Duration 6 months (Aug 2012 to Dec 2012)

Used - Tools / IC Station (Mentor Graphics) [pic] LVS, Schematic

Operating Sys. Layout Editor [pic]

Linux / Windows

Project In this project 1-bit Dual Port SRAM Cell designed &

Description developed using IC Station of Mentor Graphics along

its - Sizing, Optimization, Delay Analysis, Layout

creation for 8T SRAM Cell, LVS, DRV Check, RC

extraction. Implemented Features:[pic] Area

efficient[pic]Low Power Consumption [pic] Can be

configured up to Transistor Level.

PROJECTS UNDERTAKEN

Title Project 1: DESIGNED Amba USING VERILOG

Tools/ Used Modelsim [pic]Windows [pic]Verilog

Project In this project Amba was defined using verilog

Description language. The Advanced Microcontroller Bus

Architecture (AMBA) is used as the on-chip bus in

system-on-chip (Soc) designs.AMBA High-performance

Bus (AHB) that is a single clock-edge protocol

My RTL Coding of AMBA done by using Verilog language &

Contribution Modelsim.

Title Project 2 : DESIGNED A FIFO USING VERILOG

Tool Used Modelsim [pic]Windows [pic]Verilog

Project In this project a synchronous & symmetric FIFO was

Description defined using Verilog language. A circuit which

gives output in form of First In First Out i.e. data

which comes first at input is the first one that

goes out.

Title Project 3: DESIGNED A TIMER USING VERILOG

Tool Used Modelsim [pic]Windows [pic]Verilog

Project In this project a 3 mode TIMER was designed using

Description verilog language. In TIMER circuit it allows three

different modes. For each mode, a certain value can

be loaded.

B.Tech Projects/Training

B. Tech Major Project

Title Infra Red Based Obstacle Avoiding Robot

Language/Skill C, C++ Embedded System; using 8051

s Microcontrollers /

IR Transreceivers; & used - u-vision Keil for

coding.

B. Tech Minor Project

Title Lead Acid Battery Charger With Voltage Analyzer

B. Tech Summer Training Project

Title Electronic Alarm Clock using Verilog with HP

Awards & Recognitions

* Achieved "quick learner and fast ramp" recognition from wherever I

have worked.

* Attended workshop on Semiconductor EDA Tools by Cadence at Park, New

Delhi

* Attended Advanced Analog & RF workshop by IEEE at ST Microelectronics,

Gr. Noida.

* Got appraisals & accolades from Management & Students while training

them.

* Won IInd Prize in School XIIth class with 4 distinctions and 2 above 90%

marks.

* Won & Participated in several National Olympiads for Science, Cyber &

Math's.

* Won Certificate of merit from class I, class VII, VIII and XII during

schooling.

* Been excellent & active chess player during schooling & won many prizes

and certificates including Sub-Junior Championship, Inter School

Championship, and Open Rating Championship etc. & represented School and

Zone at State Level.

* Represented college for chess in Intra College Sports Competition of

GGSIP University 2007, 2008. 2009 & 2010 and won 2nd & 3rd Prizes

My Objective Is - To work in a creative & challenging environment where I

can utilize my skills and sharpen & improve them to compete with the future

advancements while constantly learning and successfully delivering

solutions to problems. And of course, learning is an unending process & I

am ready for it.

Personal Details

Gender MALE Marital Status Single

Date of Birth 26.10.1987 Nationality Indian

Pan Number AMZPA 2049 N Driving DL-082**********

License

Hobbies Playing Chess - my most favorite hobby specially

blitz

Online Games - playing all kinds of action & puzzle

games

Watching Movies - to watch action, comedy &

thrillers

Listening Music - to all kinds of music

Strength [pic] Simple & Sober

[pic] Adaptable

[pic] Skilled to work under pressure

[pic] Sincere & Honest

[pic] Strong Managerial & Interpersonal Skills

[pic] Quick learner

Contact H.No.- 3 / 72, 3rd Floor, Nirankari Colony, Delhi -

Address 110009. India

I hereby declare that the above mentioned information is correct up to

best of my knowledge and I bear the responsibility for the correctness of

above mentioned particulars.

(Sachin Raj Aggarwal)

Date : 25th December, 2012

Ph.(mobile): 928-***-**** - 925*******

Place : New Delhi (India) e-mail id -

abnxqv@r.postjobfree.com[pic]

Contact this candidate