RESUME

Name: MRITUNJAY BIHARI SINGH

Mobile: +91-981*******

E-mail: abmm6t@r.postjobfree.com

OBJECTIVE:

Looking forward to a challenging and competitive work atmosphere leading to a professional experience with

dynamic and progressive organization where my skills, talents and abilities will be utilized to the fullest for mutual

benefit.

PERSONAL DETAILS:

Name Mritunjay Bihari Singh

30th September 1989

Date of birth

Father’s name Dr. Simal Bihari Singh

Pan Card number CSUPS3181A

Languages Hindi, English

Correspondence Address 8 c, new layalpur extension, near gopal park gurudwara,

delhi-110051

EDUCATION QUALIFICATION:

A. Master of Technology:

University : North Maharashtra University, Jalgaon, Maharashtra.

College : Department of Electronics Engineering & Technology.

Stream : VLSI Technology.

Status : Pursuing with three semesters CGPA score of 6.53.

B. Bachelor of Engineering:

University : Solapur University, Solapur, Maharashtra.

Institute : SVERI’s College of Engineering Pandharpur.

Stream : Electronics and Telecommunication Engineering.

Examination Year Of Passing Percentage Obtained Division Obtained

Final Year of Engg 2010 74.44 Distinction

Third Year of Engg 2009 67.82 Distinction

Second Year of Engg 2008 69.63 Distinction

First Year of Engg 2007 63.65 First class

Aggregate percentage of engineering = 69.2(Distinction)

C. Secondary and higher Secondary Education:

Examination Name Of School Board Year Of Passing Percentage Obtained

XII K.V.Tawang C.B.S.E. 2006 70.6

X K.V.Samastipur C.B.S.E. 2004 78.8

SOFTWARE ORIENTATION:

1. Knows tools like Xilinx, Microwind, Hspice, modelsim, and Proteus.

2. Familiar with programming language like C, C++.

3. Familiar with simulation software like Matlab, Pspice, and Keil.

KEY SKILL:

Have worked in 1. Backend design in VLSI on Microwind, HSPICE.

2. Frontend design in VLSI on Xilinx and Modelsim.

Have taken training in Hardware Descriptive/Verification Languages: VHDL, Verilog HDL, SystemVerilog.

PROFESSIONAL ACTIVITIES AND EXPERIENCE:

Academic Projects:-

Project name: “Content based image retrieval using wavelet transform ”, on “MATLAB”.

About Project: It is an approach to retrieve an image from library or directory by CBIR retrieval method where energy

and standard deviation of image is calculated using filters on Matlab tool and are used to retrieve the image.

Time period: 1 year.

Project name: “electronic eye: an alarm”.

About Project: A small scale project using discrete circuit elements mounted on PCB where we used an IR sensor to

detect a motion and raises an alarm.

Time period: 6 month.

Project name: “design and simulation of op-amp” on HSPICE.

About Project: The operational amplifier was designed and simulated in HSPICE software by using 130nm

technology. This has dual power supply (-2.5v, 2.5v). Op-amp has very less standby power consumption as compared to

BJT because it uses CMOS technology.

Time period: 6 month.

Project name:” Design of Digital Clock with alarm using Verilog”, on Xilinx and modelsim.

About Project: it is a design of user interface for 12 hour and 24 hour clack pattern with a provision of alarm

raise and time set for alarm.

Time period: 6 month.

Project name: “Design of Digital Security Control System Using I2C communication protocol in Verilog”, on

modelsim and Xilinx.

About Project: A project to implement I2C communication protocol in security system interfaced to real time clock and

sends a code given through a 4x4 keypad by end-user.

Time period: 1 year.

Training Projects:-

Project name:”Design of 16-bit Microprocessor in VHDL” on modelsim.

About Project: It’s a general central processing unit RTL design interfaced with a memory unit which stores the

command to be fetched in it. It operates some basic functionality and design of its part like ALU, control units, register

array, comparison block etc.

Time period: 6 month.

Project name: “16 bit vedic multiplier in VHDL” on modelsim.

About Project: A VHDL coding to design a complex multiplier utilizing “ Uradhva-TIryakbyham sutra “ meaning

vertically and crosswise.

Time period: 6 month.

Project name: “UART in VHDL and Verilog”, on modelsim.

About Project: Universal asynchronous receiver and transmitter designed in verilog and vhdl. The high speed parallel

to serial convertor is designed for transmitter and receiver section both.

Time period: 3 month.

Project name: “Automatic Car Parking Space Allocation System Using Verilog”, on modelsim.

About Project: It is a project with its application in industrial world. It is a design to allocate space to car to be

parked and has security alignment with real time clock.

Time period: 3 month.

Project name: “ design and implement traffic light controller on FPGA”

About Project: Designing of traffic light controller using verilog and VHDL language and emplemen the design on

FPGA SPARTEN 3E starter kit.

Time period: 6 month.

STRENGTHS:

Good grasping power and with an impressive communication skill.

Eager to learn new and interesting things.

Friendly nature with politeness and positive attitude.

Disciplined with work and life.

Believe in one thing “plan in work and work in plan”.

DECLARATION:

I hereby declare that the above mentioned information is correct as per my knowledge and I bear the

responsibility for the correctness of the above mentioned particulars.

Place: Delhi MRITUNJAY BIHARI

SINGH

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