Fangyue Zhan

*** ****** **, *********, **, *****

213-***-****

ablup6@r.postjobfree.com

Objective: Seeking a full-time position in the field of ASIC design, Verification, physical design, or computer

architecture. Expected to graduate in May 2015.

EDUCATION

M.S., Department of Electrical Engineering, University of Southern California May 2015

Course work:

EE577A&B-VLSI System Design, EE477-MOSVLSI Circuit Design, EE557-Computer Systems Architecture,

EE457-Computer Systems Organization, EE560-Digital System Design -- Tools and Techniques, CSCI570-Analysis

of Algorithms, EE554-Real Time Computer Systems

Major GPA: 3.88 / 4.00

B.S., Department of Electrical Engineering, Beijing University of Technology July 2013

Major GPA: 3.87 / 4.00

SKILLS

Verilog, Perl, C/C++, system C, Cadence Virtuoso, Synopsys Design Compiler, Modelsim, TetraMax, Encounter,

PrimeTime

ACADEMIC PROJECT

Oct 2014 – Dec 2014

DDR2 & DDR3 SDRAM Controller Design (Verilog, DC, Encounter,Prime Time)

Designed DDR2 & DDR3 Controllers, supporting commands e.g. Scalar Read/Write, Atomic Read/Write and

Block Read/Write, etc.

Conducted simulation, synthesis, place&route, timing analysis with NC-Verilog, DC, Encounter and Prime Time.

Performed functional and timing verification to verify the design.

Layout Router Design (Verilog, Synopsys Design Compiler) Sep 2014

Designed a layout router based on Lee’s algorithm.

Detected whether grid cells in the grid were available to use or not, because of existing obstacles (logic or wires),

connecting two pairs of source and target cells on four routing layers.

Synthesized the design using Synopsys Design Compiler.

Parameterized Parallel Cyclic Redundancy Check (CRC) Design (Perl) Sep 2014

Generated the parameterized CRC modules with the user-defined data width and polynomial function.

Automatically generated the test bench of the design using perl.

April 2014 – May 2014

General Purpose Multi-cycle CPU (Cadence, Perl)

Designed a 64 bit Multi-cycle CPU using Cadence Virtuoso tools both for schematic and layout. The CPU can

implemented some basic instructions: AND, OR, ADD, XOR, STORE, LOAD, DIV, NOP. The memory in the

CPU was a 1k size SRAM.

Instruction fetch was done using software method by Perl which generated a control signal vector file to make

the whole CPU work in order.

Besides the correct function, power*delay*area was also the optimizing goal.

My team was the top four among 60 to 70 teams in the class.

Multi-Processor System-on-Chip (MPSoC) Data Transmission Router (Cadence) Nov 2013-Dec 2013

Designed both schematic and layout for MPSoC using Cadence Virtuoso tools. The network used Bitonic

method to achieve resource allocation based on the priorities of the four data transmitters.

Optimized its delay, power and area.

RTL coding of a 5-stage pipeline (Verilog) Dec 2013

Completed coding the data path and control unit of a 5-stage pipeline.

EMPLOYMENT

Verification Intern Jan 2015-now

Kopin Corporation, Inc., Santa Clara

Testing ASIC SOC functionality and performance

Test prototypes and development board

Contact this candidate