Darshan Dehuniya

Mo. +91-812*******

Email : ablfu9@r.postjobfree.com

Career Objective

To be associated with a semiconductor industry that provides me boundless growth

opportunities and exposure to cutting-edge technologies and learning possibilities.

Experience (1 Year and 5 month )

13 months ( Jan-2014 to Current) experience with Aceic Design Technologies as

ASIC Verification Engineer

4 months (June-2013 - September 2013)training at Maven Silicon

Summary Of Qualifications

Good understanding of the ASIC and FPGA design flow

Experience in writing Test benches in System Verilog and methodologies like

UVM, OVM.

Working Experience with Bluetooth Low Energy 4.1.

Very good knowledge in verification methodologies, especially in UVM.

Experience in using industry standard EDA tools for the front-end design and

verification

VLSI Domain Skills

HDL Verilog

HVL SystemVerilog

Verification Methodologies Coverage Driven Verification

Assertion BasedVerification

TB Methodology UVM,OVM

Bus Protocol AMBA AXI, AHB,APB

Serial Protocol SPI, I2c, UART

Wireless Protocol Bluetooth Low Energy 4.1

EDA Tool: Questa sim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design

Knowledge RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

Scripting language Perl, Shell(Makefile)

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore with ' A '

Grade

Year:Nov 2013

Bachelor of Engineering, Government Engineering College, Gandhinagar.

Gujarat Technological University, Gujarat, India Discipline: Electronics and

Communication Engineering Percentage: 7.35 C.G.P.A with Distinction

Year: May 2013

H.S.C. (10+2) : Shree Sharda Higher Secondary School

Secondary Education Board

Percentage : 83.20 %,distinction

Year :May 2009

VLSI Projects

Modules worked on Activities

Understanding the specification

Bluetooth VIP

(BLE 4.0/4.1) Verification plan development in Questasim readable

format.

Role: Verification Test case Preparation of Register lists,Variable lists

HVL: System-Verilog and BLE Frame list

Developed AHB Slave BFM individually which

EDA Tools: Questasim

takes information from the HOST and updates the

Methodology: OVM

Register Model

Developed INIT, NON_CONN_IND, UPDATE

ADV Channel Behavioral Model as part of TB

Development

Developed Sequence-item, constraint, base level

sequence, virtual sequence and Test cases

AMBA-AHB UVC Developed class based verification environment for

multiple masters multiple slaves (maximum 8

Role: Verification masters, 8 slaves) using UVM and OVM.

HVL: System-Verilog Implemented interconnect module for arbitration.

EDA Tools: Questasim Developed Driver functionality for Master and Slave

Methodology: UVM & OVM Developed Monitor, Scoreboard, master sequence,

virtual sequence

Master supported features like OK, RETRY,

ERROR and SPLIT Response

Developed Verification Plan and Testcases

Functional coverage check

Understood the AXI Protocol Specification

AMBA-AXI 3/4 UVC

Prepared the Verification Plan

Single Master and Single Slave VIP

Role: Verification

Burst mode supported are Increment, Wrap and

HVL: System-Verilog

Fixed

EDA Tools: Questasim

Data transfer for Aligned And Unaligned Address

Methodology: UVM Implemented Test cases

Constrained Random Stimulus Generation using

Sequences.

Functional and Code coverage

UART Master Core Understood the complete UART Protocol

Planned the Verification Architecture

Role: Verification UVM Based Environment (UART Core to UART

HVL : SystemVerilog Core Communication)

Methodology: UVM Implemented Test cases for verification of IP

EDA Tools: Questasim 10.0b Developed coverage model and Scoreboard for the

IP

Features Verified

1. Loop back mode

2. Full duplex mode

3. Half duplex mode

4. Break, Frame, Overrun and Parity Error

SPI Controller

Good Knowledge of SPI Protocol

Generated UVM Based Environment (Single Master

Role: Verification

- Multiple Slaves)

HVL: System-Verilog

Random Stimulus Generation

EDA Tools: Questasim

Implemented Test cases

Methodology: UVM

Features Verified

1. Full Duplex Mode

2. Different Mode based on clock phase and

polarity

3. Various character lengths

4. LSB and MSB Data transmission

Personal Details

Name : Darshan Dehuniya

Nationality : Indian

Language Known : English, Hindi,Gujarati

: 16th Aug,1992

Date of Birth

: B+ve

Blood Group

Hobbies : Playing cricket, Reading book, Solving Puzzles

Address : “103” Max PG, Near Arekere Gate,

Bannerghatta Road, Bangalore-560076

Declaration

I hereby declare that the information given here with is correct to best of my

knowledge and I will responsible for any discrepancy.

Place : Bangaluru Darshan Dehuniya

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