SNEHA D. NANJAPPA

**** ******** ***, ***********, ** abla3g@r.postjobfree.com 215-***-****

EDUCATION

Sep 2013 – March 2015(expected)

Philadelphia, PA Drexel University

Master of Science in Electrical and Computer Engineering GPA: 3.39/4.0

Hassan, India Visvesvaraya technological University Sep 2009- June 2013

Bachelor of Engineering in Electronics and Communication GPA: 3.8/4.0

COURSE WORK

ASIC Design I, II ASIC Design Lab Digital Logic Design

CMOS VLSI Design Advanced Programming Dependable Computing

Low Power VLSI Design Embedded Systems Fundamentals of systems

Analog and Mixed Mode Introduction to V HDL and Global Engineering Project

VLSI Verilog Management

TECHNICAL SKILLS

Cadence Tools : Virtuoso, Composer Schematic, Layout Editor, SoC Encounter RTL-to-GDSII

System

Synopsys Tools : STA PrimeTime, Place and Route, Design Compiler, IC Complier GUI, IC

Validator, Verification IP

Simulation Tools : OVM/UVM, HSPICE, PSPICE, MATLAB, ModelSim, XilinX ISE Design suite

: TCL, Perl, C, C++, RTL coding, VHDL, Verilog, System Verilog, Assembly for

Programming

8051

CORE COMPETENCIES

RTL-to-GDSII flow Functional and formal verification Clock Tree Synthesis

Dynamic circuit design RC Extraction and correlation Validation by regression tests

Timing Analysis Place and Route Tool Synthesis and Perl scripting

RTL design Layout, Power and Area efficient design ATPG

Physical Design Power Synthesis Unix Shell scripting

EXPERIENCE

Graduate Research Assistant, VLSI laboratory

Drexel University Jan 2014-Present

Clock Tree/Mesh Synthesis

Investigated clock networks and clock distribution architecture using Synopsys, Simulated clock trees

using Hspice, Observed and analyzed slew propagation on the tree for different frequencies and

voltages and various testbenches, Analyzed the combination of placement and clock network synthesis

stages for a better physical design and checked for reduced clock power dissipation. Researched about

low-power, high speed and variation-aware implementations.

Clock Mesh Support For Clock Tree Synthesis

Added clock mesh support to the existing clock tree synthesis algorithm using Perl scripting; Obtained

location, capacitance and circuit size information, mesh wire locations based on the user input grid sizes;

Propagated timing information from the sinks to the mesh intersection points; Generated the pre-mesh

tree and analyzed its properties.

Graduate teaching Assistant, Department of Physics

Drexel University March 2014-Present

Teaching Applied Physics for undergraduate students.

Includes weekly Labs & Recitation sessions.

Grading and proctoring for homeworks and examinations.

TECHNICAL EXPERIENCE

ASIC Design of OpenSPARC Floating Point Unit June 2014

Implemented a front end design flow includes RTL Design and formal verification

Back-end design included floor planning, maximum core utilization, effective clocking and powering

schemes, fixation of violated timing using CTS, model, worst and average case power estimation using

Synopsys IC compiler.

Inserted delay and global skew using STA Primetime.

Site Selection of a Biotechnology Manufacturing Facility June 2014

Lead a site selection project to identify a new manufacturing facility among the given locations

Analysed attributes like cultural, financial, political, construction and operational risks which affect the

site selection process; collected relevant data

Chose the best site for a manufacturing facility based on the risk and import-export analysis and case

studies

IC Design using Synopsys March 2014

Generated and analyzed clock tree skew and timing reports to determine CTS QoR using Synopsys.

Optimized the design for better area and performed routing the clock nets.

Analyzed the design for timing, logical and physical DRC and LVS violations.

Designed an IC and performed floor planning, placement, Clock tree synthesis, routing and chip finishing.

Branch Predictor Implementation March 2014

Configured and implemented Gshare and 2 level adaptive branch predictors in C++ and run the

benchmarks chosen.

Evaluated the affects of branch predictors on CPU performance using Gem5 simulator

Defensive Web Strategies & Implementation December 2014

Implementing DOM tree structure and same origin policy handling the cross-site scripting. Deploying the

jQuery methods and jQuery traversing for sorting links and data on the web with SSL servers and case

studies.

Design And Implementation of SRAM May 2013

Created a 6T SRAM memory element to store bits of data in 180nm, 90nm and 45nm using Cadence

virtuoso tool. Designed schematic and layout for elements of SRAM and performed DRC and LVS.

Analyzed transient and DC behavior and Performed Analog simulations in Cadence Spectre circuit

simulator.

Obtained 30% reduction in static leakage power and also obtained exponential variation with respect to

Temperature variation.

Free Space Optical Communication Transceiver March 2013

Designed a microcontroller based transceiver to transmit text messages encoded morse code via free

space optical communication link.

Programmed a 8051 microcontroller using assembly language programming and C. Performed tests

under different conditions and evaluated the system

Communication System Simulation August 2012

Developed a model for modulation-demodulation of signals using Simulink.

Programmed MATLAB code for modulation of signals and evaluated results with the theoretical values.

Contact this candidate