RESUME

RAMANATHAN D L

E-mail id: abl7kv@r.postjobfree.com

Mobile no: +91-860*******

Career Objective

To develop my career as an Engineer where I will be a valuable team member, contributing

quality ideas and work and where there is an ample scope for individual as well as organization

growth.

Academic Qualification

M E in VLSI DESIGN with 7.43(CGPA up to 3rd SEM) from College of Engineering Guindy,

ANNA UNIVERSITY, Tamil Nadu.

B TECH in ELECTRONICS and COMMUNICATION ENGINEERING with 58.00% from

Sri Venkatesa Perumal College of Engineering& Technology affiliated to JNTU ANATAPUR,

Andhra Pradesh.

Intermediate (12th) in Math, Physics and Chemistry with 88.30% from Vikas Junior College,

Andhra Pradesh.

State Board of Secondary Education (10th) with 76.83% from Little Flower High School,

Andhra Pradesh.

Software Proficiency

Programming Language: C Language, VHDL.

Tools: Cadence Spectre (GPDK180nm), and Tanner EDA.

Area of interest

Analog CMOS Integrated Circuit Design.

Digital Electronics.

Designed most of the basic circuits from Analog Integrated Circuits by BEHZAD RAZAVI in

Cadence GPDK180nm Technology.

Project

B Tech Project

Title: Smartcard Based System Design For Automated Bill Payments.

Description: The Objective is to design a atomizing the tax collection of road taxes on

expressways. This system replaces the present manual toll tax collection system with the

automatic electronic system. This proposed project consists of two units, namely a Master Unit

(M.U) and In-Vehicle Unit (I.V.U). The M.U. is placed at the traffic checkpoint on the

expressway where the toll tax is to be collected. The I.V.U. is in the vehicle, it contains a smart

card that holds the information regarding the vehicle`s identity (vehicle number) and balance

amount present in the card.

M E Project (Phase-I)

Title: Design of Bandgap Reference circuit with Startup circuit using Cadence Spectre.

Description: A voltage or current reference is key block in any analog systems. Such reference

should exhibit little dependence on temperature. The intended work encloses Bandgap circuit

exploiting self biased cascode current mirror architecture, achieves less drift in the stated range

of temperature. To prevent the circuit from stabilizing at an inadequate bias point, the strategy

used was the inclusion of an auxiliary circuit known as Start-up circuit. The start-up circuit is

designed in order to operate only at the starting moment, being deactivated when entering in

normal operation. The entire system is designed with Cadence Spectre designer tool in 180nm

CMOS technology with GPDK library.

M E Project (Phase-II)

Title: Design of CMOS LDO Regulator circuit using Cadence Spectre designer tool.

Description: The project work encloses a Low Dropout (LDO) voltage series regulator for a

wide load range confronting all the specified characteristics. The regulator design is approached

with the conventional set up consisting of Bandgap reference, Error amplifier and a pass element.

Error amplifier design has been organized with a PMOS mirror load configuration and the design

methodology uses a structure of symmetrical OTA, with miller compensation. A series pass

element is implemented with PMOS device to have high efficiency, low ON resistance and

voltage drop. The entire system is designed with Cadence Spectre designer tool in 180nm CMOS

technology with GPDK library.

Strengths

Ability to work in a team.

Sincere and hardworking.

Self-confidence.

Personal Profile

Name :

RAMANATHAN D. L.

Father Name :

LOGANATHAN D. M.

Date of Birth :

16-12-1988.

Gender :

Male.

Marital Status :

Single.

Nationality :

Indian.

Permanent Address :

5-58, S V KOIL st,

Pudupet, Nagari, Chittoor (Dist),

Andhra Pradesh.

Languages Known : English, Tamil & Telugu.

I hereby declare that the information furnished above is true to my best of my Knowledge.

Place: Chennai SIGNATURE

Date: (RAMANATHAN D L)

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