SEUNGMOO CHOI

*** ********, ******, ** *****

949-***-****, abk2z9@r.postjobfree.com

OBJECTIVES

Seeking a senior executive position, utilizing strong technical,

operational, and business skills.

EXECUTIVE SUMMARY

Results-driven operation director with a consistent track record of

engineering operations, supplier operation, supply chain management,

advanced device engineering, and technology development in semiconductor

industry.

. Over 19 years of experience in semiconductor industry in progressively

increased responsibility positions, including the last 9 years in

major leadership roles. Strong technical, business and contract

management background.

. Significant experience in dealing with foundry manufacturing including

wafer bumping operations. Successful record at managing a large wafer

fab Joint Venture for Lucent/Agere Systems in Singapore.

. Development and management of a P&L foundry business with several

large customers.

. Competitive analysis and benchmarking expertise in semiconductor

production and technology.

. Earlier challenges have included development and transfer of

technologies across several fabrication facilities worldwide.

. 18 US patents granted and 10 US Government Research Grants

. IBM TJ Watson Fellowship (Particle Beam Interaction with Solid

Surfaces and Thin Films) (1988-1991)

. Ph.D. in EE

. U.S. Citizen

PROFESSIONAL EXPERIENCE

CONEXANT SYSTEMS, Newport Beach, CA 2006-Date

Director of Global Operations

Hired by and reported to CTO & Executive VP of Global Operations to take

over corp technology, and to formulate/lead key strategic programs for

Operation margin improvement.

. Managed an Conexant P&L center via foundry wafer budget of $250M and

mask budget of $30M. Supported all aspects of Conexant Global

Operations.

. Achieved and maintained over 50% of growth margin over a 2 year

horizon despite of year-to-year substantial ASP errosion.

. Supported 100% of Conexant product revenue through the seamless supply-

chain management.

. Developed forward-looking cost model including wafer, die, mask,

assembly & test costs.

. Developed Operations technology roadmap and APAC Operations strategy.

. Led 65G+RF technology & design kit development program at both primary

source and secondary sources.

. Established dual source for 0.18?m, 90nm, 110nm, and 65nm products to

improve gross margin improvement and to secure wafer capacity.

. Executed 200+ product transfer for the 2nd source assembly and testing

facilities to reduce assembly & test cost.

. Established/chaired QRB(Qualification Review Board) to define process

and/or product qualification plan and to monitor the progress of

qualification process.

. Completed post IP, design, & product transaction program, resulting

from the acquisition of Zarlink Ethernet Switch product line.

. Managed vertically integration of the quality systems into Agile PLM

system, aligned with SAP.

. Managed foundry business & eng, quality systems, reliability, and

comparative analysis groups.

SPANSION, Sunnyvale, CA

2006-2006

R&D Manager

Hired by VP of Advance Memory Development to initiate our new joint

strategic technology development program with TSMC in Taiwan.

. Formulated/established exploratory device development program with new

vertical switching devices to realize <3F SQ Flash memory element for

22nm (and beyond) technology - patent-pending.

. Developed strategic goals and objectives with other senior management

teams.

. Interfaced with critical business units and technology development

partners to meet joint development timetables.

. Established technology development teams in Taiwan and Sunnyvale.

. Facilitated appropriate process information flow back to Sunnyvale in

a timely manner to help the on-going development efforts in SDC.

AGERE SYSTEMS, Allentown, PA 2001-2006

Technical Manager (2004-2006)

Promoted to manage foundry technology and business capacity planning teams:

directly supervising 9 engineers and 1 manager.

. Managed world-wide wafer suppliers and bump houses for logic, mixed

signal, high voltage, SiGe, and DRAM products. This included foundry

account management, foundry audits, quality and customer audits,

supply agreements, wafer pricing, wafer capacity planning, new product

introduction, technology assessment, program management, product

yield, technology transfer & development, and process/product

qualification. Key areas of emphasis are a) Manufacturing

productivity improvements b) design packing density improvements and

c) Cost reductions through yield improvement and improvements in

procurement.

Established foundry selection process & RTM (Ready to Manufacture)

process.

. Supported frame assembly and data transfer activities to foundries and

managed mask outsourcing activities for internal fabs and joint-

ventures to mask vendors.

. Manged yield and cost modeling groups, drove several benchmark

studies, and defined metrics and tracked-them to drive improvements in

design-densities, and probe yield across fabs and technologies.

Achieved highest score (4.3/5.0) among Agere teams in Gallup

organization/leadership survey.

Distinguished MTS (2001-2004)

Assigned to serve as technical liaison between foundries and internal

product groups

. Developed CMOS, MS/RF, HV, & SiGe technology menu, roadmap and survey,

product competitive analysis, fab compatibility matrix, and multi-

sourcing strategy.

. Led technology assessment and utilization activities for new product

introduction: product risk assessment, internal and third party IP

verification, product qualification, foundry technology form for

standard product and MPW, D0 monitoring program, PCM design program,

and internal DFM rule guideline for 90nm & 0.13?m foundry

technologies.

. Developed wafer cost model and supply agreements, and proposed yearly

budget for IC Device and Technology Dept.

LUCENT TECHNOLOGIES, Orlando, FL

1996-2000

Distinguished MTS of Bell Laboratories (2000-2001)

Appointed as a result of successful development of the best embedded memory

technology.

. Led internal technology and yield driver programs. The program

includes business contract, product design (with internal design

group, customers, and external contractors), process integration,

wafer cost analysis report, yield enhancement, and qualification

activities.

Member of Technical Staff of Bell Laboratories (1996-2000)

Hired to lead the embedded SRAM technology development.

Initiated/formulated/ developed the best E-SRAM technology.

. Introduced split-wordline based bit cell for the first time in 1998,

which has been adopted in the advanced (<90nm) technologies.

. Developed the smallest E-SRAM bit cell for 0.35?m, 0.30?m, 0.25?m,

0.20?m, 0.16?m, and 0.12?m CMOS logic technologies.

. Led E-SRAM module process integration (self-aligned contact,

borderless contact, and transistor matching), yield enhancement, FMA,

qualification, and technology transfer to internal manufacturing

facilities.

. Designed/coordinated design rule, process margin, memory

characterization, and defect-density testers, memory "on-pitch"

circuitry, and SRAM test vehicle.

SGS-THOMSON Microelectronics, Carrollton, TX

1995-1996

Device Engineer of Memory Product Group

Hired as device engineer to carry out yield enhancement and process

transfer for 16K SRAM's, 16K zero power SRAM's, 256K (5V and 3.3V) SRAM's

and 1Mb (256KX4 & 128KX8) SRAM's.

. Became engineering task force champion (identified root-cause of

0.35?m 256K SRAM low yield and 0.5?m 1M SRAM aluminum spiking).

. Performed DOE, SPC, device & process spec management, parametric &

probe data analysis.

. Worked on 0.5?m CMOS process integration and technology transfer of a

zero-power SRAM product into manufacturing facilities, including 4" to

6" conversion.

. Published an internal training manual on parametrics, functionality,

and in-line yield analysis for the device and process engineer.

ADVANCED TECHNOLOGY MATERIALS, INC., Danbury, CT

1993-1995

Research Scientist of Wide Bandgap Semiconductor Research

Hired to formulate research contracts to develop exploratory wide bandgap

semiconductor device and technology.

. Won 10 government SBIR/STTR contracts for SiC/GaN high

voltage device (DMOS, UMOS, MOSFET, IGBT, etc), MEMS, laser

and LED researches. From DOD, DOT, BMDO, DARPA, Army, Air

Force, Navy, NSF, and NASA.

. Designed, fabricated, and characterized the first working

AlN/SiC accelerometer, ultra high quality SiC N&P MOS, nickel

silicide contact to SiC with ultra low specific contact

resistance, the first GaN blue LED on SiC substrate, GaN MSM

UV detectors, and very high voltage (>2KV) SiC Schottky

barriers. Initiated SiC microwave PBT program with MIT

Lincoln Lab.

PENNSYLVANIA STATE UNIVERSITY, State College, PA

1988-1992

Technical Staff of Electronic Materials and Processing Research Lab (1992-

1993)

Hired by School of Engineering to support research activities at

semiconductor device and processing laboratories.

. Coordinated a training program on thin film transistor (TFT)

fabrication method for engineers from Samsung Advanced Institute of

Technology (SAIT).

. Fabricated/developed process technology for TFT on Corning glass

substrate to optimize electronic mobility utilizing encapsulation and

annealing processes.

. Built LPCVD, magnetron sputter, and thermal evaporator. Maintained RTA

and contact mask aligner.

. Designed and fabricated fully-depleted and partially depleted SOI n-ch

and p-ch MOSFETs to study an impact of the buried oxide on the device

performance and isolation, collaborated with Prof. P. Schmitt at

University of Miami.

Research Fellow of Dept of Electrical Engineering (1988-1991)

Sponsored by IBM T.J. Watson Research Center, Electronics Laboratory of

General Electric under University/Industry cooperative program, and GaAs

Technology Center of ITT (1992), to characterize and improve device

isolation/substrate coupling in GaAs ICs and to characterize the quality of

device isolation, created by hydrogen-implantation, using FET test

structures.

. Identified the correlation between the output conductance and the

depletion region under the FET channel and an impact of the frequency-

dependent output conductance on a large signal operation of GaAs

microwave MESFET and AlGaAs/GaAs HEMT fro the first time.

. Developed physics-based low-frequency output conductance model for

GaAs MESFET. Improved buried p-layer stability in microwave GaAs

MESFETs.

. Designed/fabricated Semi-Insulating Gate MISFET test devices to study

the isolation quality of hydrogen implanted semi-insulating layer on

GaAs.

EDUCATION

Ph.D. EE, Pennsylvania State University, State College, PA

MS. EE, NC State University, Raleigh, NC

HONOR & REWARD

Korean Government Scholarship for Undergraduate Study (1980-1983)

IBM Fellowship (Particle Beam Interaction with Solid Surfaces and Thin

Films) (1988-1991)

GE Fellowship (University Industry Collaboration Program) (1990-1991)

10 US Government Research Grants (SBIRs & STTRs) (1993-1995)

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