SAGARIKA SEETALA

**** ****** ****** ** `

E-mail: abhnl4@r.postjobfree.com

Columbus, IN 47203

Phone # 630-***-****(cell)

SUMMARY

. 3 years of coding experience in High level languages including

C/C++, C#

. 3 years of experience in Matlab, Simulink Modeling, Stateflow.

. 3 years of experience in working with communication protocols like

CAN, J1939 and using VECTOR CANalyzer, CANoe, CANape.

. Experience in working with SAE J1939, ATA protocols.

. Experience in designing, implementing and testing the Controls

Systems algorithms.

. Experience in using version controlling tools like Rational

Clearcase.

. Experience in working with OBD Faults, Readiness, Test Results

and In Use Ratio.

. Involved in all phases of software development from design to

maintenance

. Working knowledge in control systems, embedded software, real time

operating systems

. Good knowledge of High-level hardware and software debugging

using debuggers, oscilloscopes, logic analyzers, and simulators

. Excellent Analytical, Communication, Team and Interpersonal skills.

EDUCATION

. Masters in Electrical Engineering, Aug.2008-

Nov2009,

Wright State University, Dayton, OH GPA: 3.5 (4.0)

. Bachelors in Electrical Engineering, Oct.

2003-May 2007,

Acharya Nagarjuna University, India. GPA: 3.98(4.0)

TECHNICAL SKILLS

Engineering tools Matlab/ Simulink, Lab View&Test Stand

Programming Languages C, C++, C#, and Visual Basic

Hardware Descriptive VHDL, Verilog HDL

Languages

Platforms Windows 98, 2000, XP, MS-DOS, UNIX,

Web Servers IIS (5.1/6.0)

Modeling Languages & UML, MS Visio 2003.

Tools

Statistical analysis SAS 8.2; MS Excel.

Version Control Tools Rational Clearcase, Microsoft Visual Sourcesafe

Application Packages Dream Weaver, Pspice, Hspice, MAGIC, MATLAB/SIMULINK, MS

Office, MS Access,

Communication Protocols CAN, J1939 using VECTOR CANalyzer

INDUSTRIAL EXPERIENCE

Client: Cummins Inc Columbus, IN

Apr'10- Till Date

Employer: Magnalinea Corporation

Role: Controls software Engineer

Currently working as an Embedded Controls Engineer (Contractor) in Cummins

Emissions Solutions on the requirement analysis and control software

development for the Cummins Aftertreatment Control Module on the Paccar and

DAF engines to meet 2013 Emission Regulations.

Responsibilities:

. Requirement Analysis, Development and validation of the software code

for the DAF Aftertreatment control module.

. Develop real time embedded control solutions for automotive

application;

. Develop model based controls through simulation and implement the

design using AutoCode

. Developing and simulating the control modules in Simulink and

generating code using Real-Time workshop.

. Develop Test software procedure for algorithm using Matlab

(2008a/2010a) Simulink.

. Experience in working with the Matlab (2008a/2010a) Simulink

blocksets.

. Experience in working with all the Stateflow objects including

defining the states (both parallel and exclusive), transitions,

events, Data and actions.

. Designed the modules or enhanced the existing modules and

functionalities in C as per the requirements from TeamCenter.

. Using Clearcase for source code control.

. Experience with the FMEA and DVP&R processes.

. OBD algorithm development/implementation/testing (on test bench, in

test cell and on vehicle).

. Support in reviews of DAF diagnostic algorithms

. Development of CAN Calibration Protocol (A2L) on CANape for DAF

. Work with the CES OBD lead to establish the fault accommodation

strategies related to the Aftertreatment system controls.

. ScanTool Interface Development with Integrating Cummins OBD handlers

on DAF engine.

. Participating in the allocation of system requirements to components

. Working with software configuration management tools (Clearcase, vob,

branches)

. Working with of Clearquest problem tracking system

. Using engineering monitoring tool (Calterm) for Testing.

. Using of build tools and makefile scripts

. Using C2ST database for configuration

. Knowledge of the OBD base handler and OBD Admin Handlers.

. Knowledge of the DM5, DM26, DM7 & DM30 messages.

. Good Knowledge of IBM Rational DOOR for requirement management.

. Debugging of test benches and Software/Hardware, harness issues.

. Developed Hardware-in-loop setup using Simulink/xPC to test complex

transmission closed loop control features

. Making reports of diagnostic procedures, verification and validation

results using MS Office and presenting among the project members

through power point presentations.

HSM Solutions Peoria, IL

Nov '09 - Apr'10

Role: Test Engineer

Responsibilities:

. Developed the Test Cases for the application

. Performed Regression Testing and Unit Testing.

. Performed Test Plan Analysis based on the requirements

. Studied the data link traffic on CAN for the debugging purposes.

. Making reports of diagnostic procedures, verification and validation

results using MS Office and presenting among the project members

through power point presentations.

. Performed CPU load tests and module tests for the ECU'S

. Implemented the MAP (Memory Access Protocol) Library on the J1939

Datalink for Tier IV Displays.

. Used LAUTERBACH with TRACE32 debugger for debugging the code.

. Used Labview/Test Stand for automating the regression test.

. Defining the Requirements and designing the architecture of the

Tool

. Used Managed C++ and Unmanaged C++ for developing the features.

. Used Visual Studio 2005 IDE for the development of the Tool called

"Builder Tool" which is used for building the software.

ACADEMIC EXPERIENCE

Graduate Research Assistant, Electrical Engineering Department

(May 2009 - Dec 2009)

Wright State University

. Worked with the 3-D transistors and incorporation of them in to the

microcontrollers

. Used Flexfet in the microcontrollers.

. Tested the application by changing the modules in C++

Academic Design Projects

Worked in designing Mp3 encoder and the Decoder using the Verilog Hardware

Descriptive Language and C++ language and implemented it on an Altera DE2

board.

. Worked on the data compression modules in C++ for implementing the MP3

. Determined the address decoding logic for my proposed circuit using

various logic gates.

Designed a 4-Stage pipelined 32 bit Reduced Instruction Set Computer (RISC)

Processor using Very high speed IC Hardware Descriptive Language and C

. Developed the modules in verilog for implementation of 4-stage

pipelining

. Implemented the processor on a FPGA

. Written C code for signal processing in the RAM

Implemented the IEEE paper Design of IIR Eigen filters in the Frequency

Domain using Maple and Mat lab.

. Simulation of a Matlab code for implementing the logic of IIR Eigen

Filters.

. Simulation of Matlab program for estimation of signals corrupted with

noise based on 'IIR filtering technique'.

. The frequency domain calculation is done by using the mathematical

software Maple

Comparison of Dynamic Routing and Wavelength Assignment Algorithms in

Optical Networks

. The algorithm of signal processing inside the Optical fibers was

implemented in C

. Used Matlab simulation for the analysis of the signal strengths and

the phases

Worked on" Optimum design configuration for 35 nm Flexfet device", at

Wright StateUniversity.

. Used Silvaco tools for the Id-Vg characteristics analysis of the

transistor

. Worked with the Pspice for the Electric circuit analysis

Developed a Fault Diagnosis method in Field Programmable Gate Array

Interconnects (FPGA) using Very high speed IC Hardware Descriptive Language

and C

. The Complete test code for testing the interconnects of FPGA was

written in C

. All the possible interconnects are identified

. The Complete circuit was implement with VHDL

RELEVANT COURSE WORK

. Network Systems: Optical Networks, Wireless Communication Systems

. Communications: Signal Analysis, Telecommunications

. Circuit Design: Analog Circuits, Network Theory

. Digital Design: High Performance Embedded system design, Digital Systems

. Control Systems: Linear Control Systems

ACHIEVEMENTS

. Microsoft Certified Technology Specialist in Application Development.

. Qualified in All-India Graduate Aptitude Test in Engineering Examination

Conducted by Indian Institute Of Technology, (IIT) Mumbai With 91%.

. Got 9th Rank in Indian National Level Science talent and Research

Examination

ACTIVITIES

. Committee Member of Indian Association of Dayton (IAoD), Aug 2008 - Dec

2009

. Student member of IEEE Student chapter at Wright State University, Jan

2009-Dec 2009.

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