PURNIMA YARLAGADDA

*** ***** ***** **, abh7ep@r.postjobfree.com

Folsom, CA 95630 704-***-****

An articulate, result-driven hardware verification engineer with a unique drive for excellence

and efficient problem solving skills

OBJECTIVE

Seeking a challenging position in the fields of module or system level verification where I

can apply and enhance my skills

EDUCATION

Bachelor of Technology (Electronics and Communications Engineering) May 2006

Jawaharlal Nehru Technological University, Hyderabad, India

GPA – 83%

TOTAL EXPERIENCE

About 5 years in front-end System on Chip (SoC) and module level IP verification.

SKILLS AND ABILITIES

• Complete knowledge of single IP/ module level verification

• Proven ability in multiple aspects of SoC verification

• Expertise in eRM compliant Specman verification environment creation

• Working knowledge of System Verilog and VMM

• Well versed with ARM11 processor's Trust Zone architecture and its security features

• Considerable knowledge in psl based formal verification

• Good knowledge of SV assertions

CORE TECHNICAL COMPETENCIES

• Languages : e(eRM), psl, VHDL, Verilog HDL, System Verilog(VMM), C

• Tools : Specman Elite, Modelsim, VCS simulators, Cadence IFV, Debussy

• Scripting : Perl, Python (basics)

• Protocols : OCP, AXI, I2C, SPI

AWARDS and RECOGNITIONS

• Recipient of ‘Achiever of the Quarter’ award from Sasken for Jul-Sep 2007

• Paper written on C to e conversion methodology (enhanCE) was selected for the Texas

Instruments World Technical Conference

• Was the recipient of ‘BEST STUDENT AWARD’ from the Indian Society for Technical

Education (ISTE) for the year 2004

• Received multiple spot awards within the team

RELEVANT WORK EXPERIENCE

JBIG(IP) VERIFICATION

Sr. Verification Engineer

Sasken Communication Technologies

Duration : 7 months (Jan 2010 – July 2010)

Location : SASKEN Communication Technologies, Bangalore.

JBIG is a lossless compression standard used for coding and decoding of bi-level

images primarily. This JBIG, in particular, was designed for sequential coding and

decoding of 1bpp images.

• Integrated all the available submodules of the IP

• Created a verification plan for this module

• Created a VMM compliant System Verilog verification environment for this

module

• Developed BFMs to input the data and control sequences for JBIG

• Developed data comparison scoreboards and checkers

• Verified the design (coding and decoding) for all possible configurations and

compared against the golden reference data

DDMA(IP) VERIFICATION

Sr. Verification Engineer

Sasken Communication Technologies, Bangalore

Duration : 7 months ( June 2009 – Dec 2009)

Location : Texas Instruments, Bangalore (Wireless Division)

DDMA is a DMA engine designated for data transfers within the Display Subsystem,

which is an important IP of OMAP 4 series. Though this DMA is internal to the DSS, its

verification has been taken up as a separate task considering the enormous complexity of the

DSS.

• Involved in verification plan creation from scratch to completion

• Created an eRM compliant specman environment for the verification of DDMA.

• Coded BFMs to mimic the behavior of the video panel interface

• Implemented complex prediction of OCP 2.2 port based transactions.

• Developed transaction based and data integrity scoreboards

• Ensured 100% functional coverage

• Helped the DSS team in porting several tests to the top level.

VDMA(IP) VERIFICATION

Sr. Verification Engineer

Sasken Communication Technologies, Bangalore

Duration : 19 months (Dec 2007 – June 2009)

Location : Texas Instruments, Bangalore (Wireless Division)

VDMA is a DMA engine designated for video transfers and some on the fly data

processing. It is optimized for very low latency, right from the transfer trigger to the

actual data transactions. It is an IP designed for chips in the OMAP 4x series.

• Involved in verification plan creation from scratch to completion

• Created an eRM compliant specman environment from the scratch for Service

Engine of VDMA.

• Developed the sequences for controlling inputs at SE ports.

• Developed the constraints to generate the constrained random inputs at Service

Engine.

• Developed the prediction, checkers and scoreboarding part of the environment.

• Created the setup for Formal Verification of the 6 OCP ports of VDMA and

worked on the same

• Ensured 100% functional and code coverage of the SE of VDMA

• Worked on the complete unit level verification of a sub module, the transaction

breakdown unit

• Modified and improvised the python model of the above used for verification

OMAP 3430 – SoC VERIFICATION

Verification Engineer

Sasken Communication Technologies, Bangalore

Duration : 12 months (Nov 2006 – Nov 2007)

Location : Texas Instruments, Bangalore (Wireless Division)

The OMAP 3430 device is a high performance multimedia application processor based

on the enhanced OMAP 3 architecture integrated on a 65nm process. This architecture

is designed for wireless terminals. It is a very complex SoC with 20million gate count.

• Created specman based setups for various levels of integration checks

• Worked on Virtual Processor and Specman based register verification for all

modules in OMAP3430.

• Created scenarios for stress test of the interconnect (L3) used in the SoC

• Developed perl scripts for porting existing C libraries to Specman (high level and

register level) as well as C testcases.

• Developed a setup for automation of C testcase conversion and run in e. Achieved

2x - 4x improvement in runtime.

• Was an author of a paper on the methodology of C to e conversion and its

advantages

VIRTUAL PROCESSOR (ARM1176)

Verification Engineer

Sasken Communication Technologies, Bangalore

Duration : 2 months (September - October 2006)

Client : Texas Instruments, Bangalore (Wireless Division)

Location : SASKEN Communication Technologies, Bangalore

This is a SPECMAN based Verification IP. ARM1176 processor (core) is implemented

in 'e'-language. This is used in simulation replacing the RTL version of the same ARM

core. This results in very faster simulation time.

1. Implemented the VP integer core and interrupt handler parts.

2. Implemented the security based functions of the processor.

3. Verified the whole of the VP implementation.

I2C VERIFICATION IP

Intern

Sasken Communication Technologies, Bangalore

Duration : 6 months (October 2005 - March 2006)

Location : SASKEN Communication Technologies, Bangalore

Implemented the Verification IP for the I2C protocol using Specman.

• Developed the I2C Master/Slave BFM to interact with Slave/Master DUT

• Developed monitors and checkers

ACADEMIC PROJECT

FPGA IMPLEMENTATION OF VITERBI CODEC

Duration : 3 months ( Feb – April 2006)

Role : Project Leader for a team of three members and lead developer.

Purpose : Graduation Project

This project involves the design and implementation of ‘Viterbi’ Codec using Xilinx’s

Spartan-3 FPGA. This implementation conserves memory by featuring the use of a single

memory unit using a single pointer for trace back operation. The decoder system employs hard-

decision decoding. A convolution encoder with constraint length 3 and code rate are

implemented in this design.

• Implemented the whole design in VHDL (mixed model)

• Ensured the functionality of the same with thorough verification

• Operated on Xilinx’s ISE 8.1i for synthesizing the design

• Ported the same onto Spartan-3 FPGA.

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