RESUME

RAMALAKSHMAIAH.T

B-TECH: ELECTRONICS AND COMMUNICATION

Phone Number: +918*********, +919*********

E-mail ID: ab9h3z@r.postjobfree.com

Summary of Qualifications

> Good understanding of the ASIC and FPGA design flow.

> Experience in writing RTL models in Verilog HDL and Testbenches in

SystemVerilog.

> Experience in using industry standard EDA tools for the front-end

design.

> Good understanding of Analog design, Digital design and Physical

design concepts.

> Good knowledge in verification methodologies.

VLSI Domain Skills

HDLs: Verilog.

HVL: System verilog.

Verification Methodologies: Coverage Driven Verification

Assertion Based Verification

TB Methodology: UVM

EDA Tool: Modelsim, Questa - Verification Platform

and ISE

Domain: ASIC and FPGA Design Flow, Digital Design methodologies

Knowledge : Basic Concepts of System Verilog, RTL Coding, FSM

based design, Simulation, Code coverage,

Functional Coverage, Synthesis and Static

Timing Analysis.

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore

Year: July 2013

Bachelor of Technology

College : JAGANS A.P.

Discipline : ELECTRONICS AND COMMUNICATION ENGINEERING

Percentage : 66.77% (First Class)

Year : July 2012.

Achievements

. Certified in National Mathematics Talent Competitions.

. Participated in C-quiz in National level Technical Symposium in V@TOR

at AUDISANKARA college of engineering and technology

Experience

April 2013- August 2013, Maven Silicon, VLSI Design and Training Center

VLSI Projects

> Dual Port RAM - RTL design and verification

HDL: Verilog

HVL: System Verilog

EDA Tools : Modelsim, Questa - Verification Platform and ISE

. Implemented the Dual Port RAM using Verilog HDL

. Architected the class based verification environment using System

Verilog.

. Verified the RTL module using System Verilog.

. Generated functional and code coverage for the RTL verification

. Synthesized the design.

.

> FIFO - RTL design and verification

HDL: Verilog

HVL:UVM

EDA Tools : Modelsim, Questa - Verification Platform and ISE

. Implemented the FIFO Design using Verilog HDL

. Architected the class based verification environment using UVM.

. Verified the RTL module using UVM.

. Generated functional and code coverage for the RTL verification

. Synthesized the design.

> Router 1x3 - RTL design and Verification

HDL: Verilog

HVL: UVM

EDA Tools: Modelsim, Questa -- Verification Platform and ISE

Description : The router accepts data packets on a single 8-bit port called

data and routes the packets to one of the three output channels, channel0,

channel1 and channel2.

> Architected the design and described the functionality using Verilog

HDL.

> Architected the class based verification environment using UVM.

> Verified the RTL model using UVM.

> Generated functional and code coverage for the RTL verification sign-

off

> Synthesized the design

Engineering Project

Project Title : OBJECT DETECTION AND TRACKING

Languages used : MATLAB

Description : Object detection & tracking in

general, is a challenging problem. Easily we can detect the object but

Difficulties in tracking objects can arise due to abrupt object motion,

changing appearance patterns of both the object and the scene, non rigid

object structures, object-to-object and object-to-scene occlusions, and

camera motion. Tracking is usually performed in the context of higher-level

applications that require the location and/or shape of the object in every

frame. Major application is Traffic Surveillance and Hostile Aircraft.

References

On Request

Personal Details

Father's Name : T.Ramalakshmaiah

Date of Birth : 05-02-1990

Gender : Male

Nationality : Indian

Declaration

I consider myself familiar with VLSI System Design Engineering

aspects. I am also confident of my ability to work in a team. I hereby

declare that the information furnished above is true to the best of my

knowledge.

(RAMALAKSHMAIAH.T)

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