Aboli Barve

**** ********* **,*******,** *****. (1-713-***-**** .

ab1rnt@r.postjobfree.com

OBJECTIVE

Seeking challenging and rewarding software/hardware position in electrical

and computer engineering areas.

INDUSTRY PROJECTS

FirmwareTest Engineer at IBM for CTG (July 2012 - April 2013)

Power System platforms : 770, 780

Tools : VIOS, Red-Hat Linux, Linux SuSe, AIX, i5 -OS, Rational

Function Tester (RQM), Perl, Python

Performed miscellaneous lab supports tasks, including Managed system

setups, VIOS, AIX, i5-OS updates on Logical Partitions. Updated many

service-packs on Power 7 and Power 6 systems

Performed service-pack testing for XM bus component of Power Hyper-visor

for DLPAR and Partition migration testing.

Documented test procedures and setup-environments for VIOS, Active Memory

Service (AMS) and updated test execution records in RQM.

Opened and integrated many firmware and hardware defects using Clear Quest

while LED, Op-panel and automated unit testing.

Performed and documented Concurrent Code Load and Concurrent Hardware

Manage Testing for service-pack

System Validation Engineer at Freescale Semiconductor (July 2011 - June

2012)

1G-10G NAS and ISCSI SAN reference design solution

QorIQ Highspeed Multicore Silicon Reference Designs:P2041RDB, P3041RDB,

P5020RDB

Test Centers : Spirent Test Center, HP Server

Benchmarked the write and read speeds of SSD, SATA and SAS HDD for local

RAID 0, RAID 1, RAID 5, RAID 6 against various file-systems

Worked on performance testing of 10G-15G traffic using XAUI cards, Intel

NIC cards, RAID accelerations PCIE 2.0 gen2 cards.

Developed scripts for building NAS and ISCSI SAN test-bed on BSP images.

Analyzed results obtained by running Iometer, Iozone, Robocopy, and

Crystal Benchmark disk speed testing tools on software and Hardware RAID

engines in silicon.

Achieved a sustainable and stable 300-400MB/s Read/Write NAS and SAN

solutions

Network Benchmarking

QorIQ Silicon Reference Designs:QorIQ (P102x, P2040RDB), PowerQuicc

(8308NSG)

Test Equipment Involved : PCIE Analyzer, Smartbits 600B,

Spirent Test Center

Executed performance testing of QorIQ and PowerQuicc platforms supporting

Linux kernels 2.6.32 and 2.6.35, 3.0.6.

Derived the test plans, performance-test reproducibility guides, and quick

start guides which helped Field Application Engineers to run demo of the

platform performance results for boosting sales of silicon.

Generated test results for IPV4, IPV6, VLAN, L2 bridging, NAT-Firewall, LM

benchmarking, IPSEC (ESP and GRE tunneling), Wi-Fi 802.11 a/b/g/n to

silicon customers.

Technically performed the integration of the Freescale developed

Application Specific Fast Path modules into the OpenWrt image for enhancing

30% of IPV4 and IPSEC performence.

Demonstrated the using of OpenWRT applications like DLNA (mini DLNA

server), NVR (Live555 server), WVOIP(SIP server- Asterisk software). Run

iXChariot to prove the performance test results which showed sustainable

250-700Mbps wireless and 1G-10G Ethernet data flow.

Research Assistant, University of Houston, Houston, TX (Jan 2011-June 2011)

Automated foveal center detection: 9nm AOLSO retinal image

Developed and implemented signal processing and communications Algorithms

in MATLAB's simulink.

Implemented Fast Distance Transform, Watershed Transform, Voronoi Analysis

and Contour Plots in C and Matlab to find peak density of the retinal image

and retinal hexagonal-cone spacing.

Product Design Intern, EPS Worldwide Pvt. Ltd., Pune, India (Jan 2006-

June2007)

Stand Alone Spray Fluxer Unit

Designed and fabricated the embedded control system for automated fluxing

of PCBs.

Designed the pulse width modulation schemed in the Pulse to Voltage

convertor DC drive for 40kgcm, 12V Mitsuba DC motor, input:80c552 PWM

Wrote C and assembly codes for controlling the IO of system peripherals

like 4x1 keypad, 40x2 40200 LCD, 16bit 93C46 serial ROM, 1.8 Stepper Motor

and drive, DC motor.

ACADEMIC PROJECTS

Verilog HDL (Course: Advanced Hardware Design)

Wrote RTL Verilog codes and developed test benches for simulation in

Modelsim. Using Quartus II software to compile the approved RTL

software for real time implementation of FPGA in Alter DE2 board.

Variable Length Header Processor

Developed FSM for conversion of variable length packet header received from

the network to fixed length packets.

Implemented module of ROM for storing the first two packet headers

received, for bytes at each clock

Designed a FSM for the pipelined buffer to convert the variable data fields

into fixed data fields

Implemented the RAM module to output the data converted four bytes at each

clock.

Matched Filter Design For Noise Reduction and Signal Peak Detection

(Course: Stochastic Processes - Digital Signal Processing)

Calculated the mean standard deviation and central moments to document the

noise properties.

Plotted Histograms to verify the Gaussian behavior of noise data .

Designed a time -average filter of optimum length to filter Gaussian noise

and studied the effect of length of filter on variance of filtered noise .

Implemented the matched filter to detect the center of pulses and their

respective amplitude

EDUCATION

. Master of Electrical Engineering (GPA 3.69/4.0)

University of Houston, Texas, Aug 2008 - Dec 2010

. Bachelor of Engineering - Electronics & Telecommunication (GPA 3.83 /

4.00)

University of Pune, India, Aug 2003 - May 2007

SKILLS

C, Verilog, Assembly language for 8086/8051, Perl, Python, Objective-C

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