Senior Design Verification Engineer

The position involves deploying UVM/C based Testbenches for multi-core, multi-threaded processor-based chips with emphasis on Power/Performance KPIs sign-off along with quality functional verification. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM or proprietary processor technology and AMBA AHB/AXI/APB protocols along with peripheral interfaces like SDIO, UART, I2S, I2C, PWM.

Responsibilities

Develop and execute chip level test plan to meet product requirements.

Tests will be a combination of directed (C tests), constrained random (UVM), and formal SVAs.

Complete coverage closure, grading, and analysis.

Setup and debug UPF simulations at SoC and Subsystem level.

Perform gate level verification across corners and provide activity files for power analysis.

Proven record of accomplishment in finding system level bugs

Mentor global teams and provide technical leadership for AMS verification.

Skills You Will Need

8+ years in Industry.

Bachelor's or Master's degree in electrical and/or Computer Engineering

Strong knowledge of Verilog, System Verilog, UVM, C/C++.

Advanced verification skill in SVAs, constrained random stimulus and coverage analysis.

Knowledge of scripting languages like Perl, Python, Tcl, shell.

Knowledge of C Based Testcases.

Debug SDF Back Annotated Gate Simulations.

Verify and debug low-power design with UPF.

Mixed Signal Real Number Modeling (RNM, Spice).

The following qualifications will be considered a plus:

Knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture.

Knowledge of high-speed interfaces like Quad/Octa-SPI.

Advanced verification skill in SVAs, constrained random stimulus and coverage analysis.

Mentoring and leadership skills.

Exceptional problem-solving skills.

Good written and oral communication skills.