Design Verification Engineer

Position: Design Verification Engineer

Location: Austin, TX (Onsite/Hybrid)

Position Overview:

5+ years of relevant experience in Design Verification.

Experience with System Verilog and UVM is a must.

Strong experience in testbench development such as UVM methodology.

Knowledge of GPU, experience with Shader, Texture, or Memory System a plus.

Education: Bachelors Degree in related field.