Senior Design Verification Engineer

Qualifications

Proven track record of success in verification strategy development and execution for large SoC’s, and signoff with coverage metrics

Hands-on knowledge of UVM methodology, System Verilog, C/C++

Implement directed and constrained random test benches for communication physical layer, Ethernet networking, packet processing, and multi-CPU environments

In-depth understanding of networking standards, bus protocols, high-speed serial link protocols

Experience with CPU instruction set testing and cache coherent system testing

Knowledge of verification IP and functional coverage techniques

Experience with gate-level simulations of delay annotated netlists

Exposure to FPGA emulation and lab validation

Project planning and execution and performing test strategy tradeoffs to achieve coverage and schedule targets

Strong leadership and experience building world-class verification teams

BS in Electrical Engineering or related + 13 years of experience, or MS + 11 years of experience, or Ph.D. + 8 years of experience