Design Verification Engineer

5 to 10 years of Experience in pre-silicon RTL Verification /IP Verification / SOC verification Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM).

Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed function units with AXI or NOC interconnects Verification of embedded CPUs such as ARM, Tensilica, MIPS CPUs and interconnect subsystem through C/Assembly language tests Verification of industry standard serial interfaces such as MIPI, USB, PCIe using industry standard VIP components.

Ethernet Packet Processors, buffer managers, DMA engines etc.

PHY layer verification of serial interfaces such as Ethernet, PCIe, USB etc.

Solid Linux environment.