Process/Characterization Engineer resume in Arlington, TX, 76013

Process/Characterization Engineer

Posted by:	Name is not set.
Posted date:	11/3/2009
Contact Info:	********@*.* Show Contact Info (premium) Send Message (free)
Country:	United States
State:	Texas
City:	Arlington
ZIP:	76013
Email:	xy3zij@r.postjobfree.com

Resume Text:

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Amit Banik.
412 S Cooper Street.
Apartment #15
Arlington, Texas- 76013.
Phone; 817-805-****
Email: xy3zij@r.postjobfree.com

Objective:
Seeking a full time which would provide me with an opportunity to strengthen my skills and knowledge and gain valuable experience in the semiconductor industry or research environment to contribute in a productive way to the corporate/educational field in the near future.

Education:
MS Electrical Engineering, University of Texas, Arlington, TX GPA: 3.6 / 4.0
• Anticipated Graduation date : [December 2009]

BE(Bachelor of Engineering), Electronics and Communication Engineering, Visveswaraiah Technological University. Karnataka, India Aggregate: First Class( 65%).
[August 2005]
Experience and Skills:
1.Cleanroom Environment Experience (1-2 years)at The University of Texas at Arlington.
[January 2008-Present]
2. Research Experience:

• MS(Thesis):Pyramidal microstructure of ZnO(Zinc Oxide) as an Antireflective coating for Solar Cell. [September 2008-present]
In this research the Zinc Oxide particles were made using silicon as a mold and electrodepositing Zinc oxide. The experience gained:
Experimental: PECVD Silicon Nitride Deposition, Sputtered Deposition of ITO, Photolithography, Wet Etching and Electrochemical Deposition of Zinc Oxide on Silicon.
Characterization: Profilometer, Ellipsometer, SEM, XRD and Spectrophotometer.
• Characterization and Packaging Experience:Mobility extraction of High-k Dielectric [January 2008- May 2008]
C-V and I-V characterization and mobility was calculated from fabricated MOSFET, MOSCAP and Hall Bar devices. Wire Bonding and Packaging was also done.
Tools Used: Electrical Test Station(Agilent 4155C and 4284A) and Kulicke & Soffa Model 4524 Ball Bonder.
3. Graduate Teaching Assistanceship Experience(GTA):

• Silicon IC Fabrication Laboratory: [September 2008-May 2009]
Guide graduate students in understanding the operation and theory of the experiments like, Thermal Oxidation, Diffusion, Photolithography and Aluminium deposition and etching was performed. Capacitors and planar p-n junction were fabricated and characterized.
• Undergraduate circuit laboratory [January 2008- May 2008]
Help undergraduate students with the implementation and realization of the circuit.
4. Experience and Skill with Cleanroom Tools:

• Characterization tools: Electrical Test Station(Agilent 4155C and 4284A), Profilometer, Reflectometer, SEM, EDS, XRD, Lifetime tester, Spectrophotometer, Solar Simulator Am1.5.
• Deposition Tools: PVD,AJA Sputter System, PECVD,Thermal Evaporator, Potentiostat. AJA E-Beam Evaporator, ( Plasma Processing).
• Etching tool: DRIE.

5. SOFTWARE SKILLS:
Simulators:
Languages:
OS:

MATLAB, PSPSICE, Cadence
C, C++, 8085 and 8086 Assembly
Windows 98/XP, Microsoft Office.

Relevant Courses and Research Paper/Projects:

• Statistical Process Control (SPC)
• Solar cell Material and Devices
• Silicon IC Fabrication Technology.
(Fabrication of MOS Capacitor and Planar p-n junction and characterizing to get C-V and G-V characteristics to get different parameters like accumulation, depletion and inversion capacitance at high frequency voltage.)
• Semiconductor Device Theory
• Electronic Materials: Principles and Applications
(Thin Film Photovoltaic:This Projects describes the physics behind solar cell and cell design, processing technology and anti reflective coating is considered with regard to thin film solar cell)
• Introduction to MEMS.
(Surface Micromachined Metallic Needles: Requirement for microneedles and the fabrication of hollow and surface micromachined metallic needles were discussed.)
• Design of XOR using CMOS Complex Logic(Fall2008):It dealt with the design of simple XOR gate with the use of CMOS complex gate and to drive a load of 50 ohm and a capacitor of 150fF.
• Design of D-Latch using CMOS Complex logic(Fall2008):The D-latch was designed using NAND CMOS Complex logic and the load was of 50ohm and 100fF.

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